Field
Aspects of the present disclosure relate generally to testing, and more particularly, to test architectures for multi-die chips.
Background
A die typically includes a test circuit for testing an internal circuit (e.g., core logic) on the die and/or testing connections between the die and an external device. The test circuit may include multiple scan cells coupled in series to form a boundary scan chain on the die. The boundary scan chain provides an external tester with access to the internal circuit and input/output (I/O) pads for testing. The test circuit may also include an instruction register configured to store instructions specifying a test setup for a test.